1. Field of the Invention
This invention relates to an apparatus and a method of operation of a dynamic random access memory (DRAM) controller useful in data processing systems, and in particular to a DRAM controller employing multiple independent control channels for processing address strobe signals.
2. Description of the Prior Art
Presently known data processing systems generally include dynamic memory arrays having storage elements arranged in rows and columns. During operation, access to selected storage elements of the memory arrays or banks is achieved by means of row address and column address signals received from a computer interface and which are applied to a DRAM controller for processing. Row address strobe (RAS) and column address strobe (CAS) signals provided by the interface act to drive a timing generator or clock that controls the timing of the output of signals to the memory arrays.
When DRAMs are used in a data processing system, special circuitry is required in the address/control path to control the DRAMs and the interface to the central processing unit (CPU). This circuitry generates refresh addresses, multiplexes row, column and refresh addresses, and drives the control signals to the dynamic RAMs. In addition, it initiates the refresh cycles at the rate that is required to maintain data in the dynamic RAMs and arbitrates between refresh and access cycles. Furthermore, the sequences of addresses and control signals that are generated by the circuitry needs to satisfy the protocol and timing requirements of the DRAMs.
In some types of prior art RAM controllers such as depicted in FIG. 1, each CAS output signal is paired with a row address strobe (RAS) output signal, so that in each access cycle, one RAS and the corresponding CAS output signals are activated. Therefore, each CAS output is connected to a different memory bank, and each memory is accessed as a single indivisible unit. Such controllers are able to access directly data words of single width only, i.e., data words of one or more data bytes, but cannot access directly an individual byte of 8 bits in a data word of 16 bits or 32 bits. The access of an individual byte in a multiple byte data word is necessary in any microcomputer system that has instructions which result in a byte-write operation, that is, writing a byte of data into one of the multiple bytes of a memory word. In order to avoid the writing of irrelevant data into the remaining bytes of the memory word, only the byte that is written to may be accessed while the other bytes are not. Currently available 16 bit and 32 bit microprocessors have byte-write instructions, and microprocessor systems thus require byte-write capability and individual byte access.
Other available prior art DRAM controllers produce a single column address strobe (CAS) output signal that is connected to a multiplicity of memory banks, as illustrated in FIG. 2 of the drawings. Therefore, only one indivisible word can be accessed directly for each memory bank. If there is a need to access part of data words, external logic circuitry is required to split the CAS output from the controller and to create separate CAS signals for the separate bytes of the data word. In addition, external driver circuitry is needed to drive the CAS lines. The external logic and external driver circuits add to the chip count of the system and lengthens the propagation delay of CAS signals, on the order of 40 nanoseconds or more, which tends to degrade system performance.
In those systems in which error detection and correction are implemented, separate controls are generally required for the data memory and the check bits. Thus, more than one CAS or more than one write enable (WE) signal is needed to provide independent control of the data and separate independent control of the check bits.